The present invention relates to an integrated circuit, and more particularly to a field-programmable logic array (hereinafter abbreviated as FPLA) that can be realized in the form of a monolithic integrated circuit.
As is well known, an FPLA has been described as an LSI which can realize a random arbitrary logic circuit through the process whereby a user electrically writes (that is, "programs") the circuit freely at hand (that is, in "the field"). Similarly to a programmable logic array which is programmed by means of a mask during production (hereinafter abbreviated as "mask PLA"), an FPLA comprises a plurality of programmable element matrixes for achieving an AND-function and/or a plurality of OR-functions, and the inputs and outputs of these matrixes are connected to each other or to other input logic sections or output logic sections either directly or via buffer circuits. Moreover, in an FPLA there are provided selection circuits for programming the rows and the columns, respectively, of the programmable element matrixes so that any bit in the programmable element matrixes can be programmed in the field, unlike the simple mask PLA. Accordingly, in general, along the periphery of the programmable element matrixes must be disposed respective circuits in a logic system and respective peripheral circuits for programming in correspondence to the rows and the columns, respectively, of the element matrixes. This brings about serious problems especially in the case where an FPLA of large capacity is to be designed. As one problem, generally in a large-capacity and high-density FPLA, whereas the rows and columns of the programmable element matrix are arrayed at a minimum pitch, in the peripheral circuit, especially in a circuit in the logic system it is difficult to design a unit circuit corresponding to one row or one column so as to come within the same minimum pitch, and if these unit circuits are arrayed along one side of a chip, then the side of the chip must be greatly expanded as compared to the corresponding edge of the programmable element matrix, and hence the design arrangement becomes inefficient with respect to a chip area.
As a second problem, in an FPLA, in most cases the input and output terminals (of the logic system) are generally connected to the programmable element matrixes directly without being decoded at all or almost without being decoded unlike a random access memory. Thus, in a large-capacity FPLA a large number of input and output terminals are necessitated, and these terminals are compelled to be disposed along the entire periphery of the chip. However, if a peripheral circuit in the logic system is disposed close to one edge of the element matrix then in order to connect to the input or output of the peripheral circuit, most of the large number of input or output terminals must be connected through long wirings along the periphery of the chip, and this is also inefficient with respect to a chip area in the design of arrangement and with respect to performance.
As a third problem, in an FPLA also, like the conventional Programmable Read Only Memory (PROM), upon programming a large electric current must be passed through selected row and column of the programmable element matrix via programming circuits for the rows and the columns in order to feed energy necessary for programming. Accordingly, if these programming circuits for the rows and the columns are disposed close to one edge of the programmable element matrix, then for the purpose of writing in the programmable element of the matrix which is farthest from the programming circuits, a large electric current must be passed along the length of two edges of the matrix. Thus, the potential drops in the row and column wirings occurring at that time become large, and hence in some cases, the potential drops undesirably affect the writing or programming characteristics. These problems are also true, besides the FPLA, in the case of the so-called non-volatile memories in which a storage effect of information is achieved by selective injection of electric charge into a floating gate or certain insulating film such as a silicon nitride film and an alumina film, etc. In these non-volatile memories, the writing necessitates means for applying a voltage to a programmable element, separately from that used upon reading, and hence the peripheral circuits and the associated input and output wirings occupy a large portion of the area of the chip.